Sampling amplifiers are used in a number of applications, one of which is as a clocked comparator. In a typical type of such circuit a reference voltage is applied to the input of the amplifier, and capacitors inside the amplifier are allowed to charge to a level to preferably bias the amplifier to a high-gain point on the amplifier transfer characteristics, with the amplifier's output voltage at a voltage between the supply voltage levels. When the reference voltage is replaced by an unknown voltage, the voltage difference between the unknown voltage and the reference voltage is amplified and the output voltage usually is pulled toward one of the supply voltages by the amplifier. Circuits of this type are well known in the art and are described in various articles including Tsukada, Toshiro et al, "CMOS 8b 25 MHz Flash ADC", Proceedings of the 1985 IEEE International Solid-State Circuits Conference, pp 34,35; and Kansy, Robert J., "Response of a Correlated Double Sampling Circuit to 1/f Noise", IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 3, June 1980, pp 373-375.
Comparator circuits of this type are very useful in CMOS flash analog-to-digital (A/D) converter circuits because of their simplicity and response time. Such a comparator circuit may include the series combination of a first series capacitor, a first amplifier, a second series capacitor and a second amplifier plus various switches and reference voltages to precondition the series capacitors during a reset operation of the comparator. Such a comparator operates by first being reset or "zeroed" to set a proper charge on the capacitors, and then by being connected to the unknown input voltage.
A significant limitation of prior art A/D converter circuits described in the previous paragraph is that the reset operation is usually repeated between every sample even though the charge on the capacitors, set by the previous reset operation, is still correct for the next and many more sampling operations, that is, until the charge leakage from the capacitors would require another reset operation. The reason for performing the reset between each sample is to quickly return the amplifier back into its narrow active range of operation after the sample and comparison operation pulls the output of the amplifier toward one of the supply voltages. In other words, if at least significant bit input signal is applied after the amplifier has had its output driven to one of the supply voltages, the time required for the amplifier to recover and provide an accurate output would be excessively long if a reset operation were not performed. Since the reset operation takes at least long enough for the amplifier to return to is settled active region, and then for the capacitors to settle out, the periodic sample rate must be sufficiently long to include a reset operation in addition to the actual sample and comparison operation.
Therefore it can be appreciated that a circuit which would provide a faster zeroing operation between samples of a sampling comparator is highly desirable.